1. Field
Exemplary embodiments of the present invention relate to an integrated circuit design, and more particularly, to a complementary metal oxide semiconductor image sensor.
2. Description of the Related Art
A conventional column-parallel CMOS image sensor (hereinafter, referred to as a CMOS image sensor or a CIS) includes a plurality of analog-digital converters (ADCs), a plurality of buffer memories, and a plurality of sense amplifiers. The analog-digital converters convert analog signals that are sensed in a pixel array, where a plurality of pixels are arrayed, into digital signals.
Herein, each of the analog-digital converters includes a voltage generator for generating a reference signal, for example, a ramp signal VRAMP, a comparator for comparing the value of pixel signal transferred from the pixel array with the ramp signal VRAMP, and a counter for counting the output signals of the comparator.
The analog-digital converter uses comparator that is formed in a cascading form to obtain a sufficient gain. Meanwhile, the counter operates by using a voltage that is different from the voltage for the comparator. That is, the counter and the comparator operate at different power domains.
According to the conventional technology, when the power domain is changed from an analog power domain of the comparator to a digital power domain of the counter, offset may occur and the gain may be deteriorated due to the voltage level difference between the two power domains.
The deteriorated gain of the comparator causes the resolution of the comparator to be decreased.
In addition, power noise is caused due to the operation characteristics of an inverter-type amplifier circuit included in the analog-digital converter and may become a concern.